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| E n n n n n n n 28F016SA 16-MBIT (1 MBIT X 16, 2 MBIT X 8) FlashFileTM MEMORY Includes Commercial and Extended Temperature Specifications User-Selectable 3.3V or 5V V CC User-Configurable x8 or x16 Operation 70 ns Maximum Access Time 28.6 MB/sec Burst Write Transfer Rate 1 Million Typical Erase Cycles per Block 56-Lead, 1.2 mm x 14 mm x 20 mm TSOP Package 56-Lead, 1.8 mm x 16 mm x 23.7 mm SSOP Package n Revolutionary Architecture Pipelined Command Execution Program during Erase Command Superset of Intel 28F008SA 1 mA Typical I CC in Static Mode 1 A Typical Deep Power-Down 32 Independently Lockable Blocks State-of-the-Art 0.6 m ETOXTM IV Flash Technology n n n n Intel's 28F016SA 16-Mbit FlashFileTM memory is a revolutionary architecture which is the ideal choice for designing embedded direct-execute code and mass storage data/file flash memory systems. With innovative capabilities, low-power, extended temperature operation and high read/program performance, the 28F016SA enables the design of truly mobile, high-performance communications and computing products. The 28F016SA is the highest density, highest performance nonvolatile read/program solution for solid-state storage applications. Its symmetrically-blocked architecture (100% compatible with the 28F008SA 8-Mbit FlashFile memory), extended cycling, extended temperature operation, flexible VCC, fast program and read performance and selective block locking provide highly flexible memory components suitable for Resident Flash Arrays, high-density memory cards and PCMCIA-ATA flash drives. The 28F016SA dual read voltage enables the design of memory cards which can be interchangeably read/written in 3.3V and 5.0V systems. Its x8/x16 architecture allows optimization of the memory-to-processor interface. Its high read performance and flexible block locking enable both storage and execution of operating systems and application software. Manufactured on Intel's 0.6 m ETOX IV process technology, the 28F016SA is the most cost-effective, highest density monolithic 3.3V FlashFile memory. November 1996 Order Number: 290489-004 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 28F016SA may contain design defects or errors known as errata. Current characterized errata are available upon request. *Third-party brands and names are the property of their respective owners. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-879-4683 COPYRIGHT (c) INTEL CORPORATION, 1996 CG-041493 E 28F016SA CONTENTS PAGE PAGE 5.6 AC Characteristics-Read Only Operations.................................................32 5.7 Power-Up and Reset Timings.....................37 5.8 AC Characteristics for WE#-Controlled Command Write Operations ......................38 5.9 AC Characteristics for CE#-Controlled Command Write Operations ......................42 5.10 AC Characteristics for Page Buffer Write Operations.................................................46 5.11 Erase and Word/Byte Program Performance, Cycling Performance and Suspend Latency.......................................49 6.0 DERATING CURVES.....................................50 7.0 MECHANICAL SPECIFICATIONS FOR TSOP ............................................................52 8.0 MECHANICAL SPECIFICATIONS FOR SSOP............................................................53 APPENDIX A: Device Nomenclature and Ordering Information ..................................54 APPENDIX B: Additional Information ...............55 1.0 INTRODUCTION ............................................. 5 1.1 Product Overview ........................................ 5 2.0 DEVICE PINOUT............................................. 6 2.1 Lead Descriptions ........................................ 8 3.0 MEMORY MAPS ........................................... 12 3.1 Extended Status Register Memory Map..... 13 4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS............. 14 4.1 Bus Operations for Word-Wide Mode (BYTE# = VIH)........................................... 14 4.2 Bus Operations for Byte-Wide Mode (BYTE# = VIL) ........................................... 14 4.3 28F008SA-Compatible Mode Command Bus Definitions.......................................... 15 4.4 28F016SA-Performance Enhancement Command Bus Definitions......................... 16 4.5 Compatible Status Register ....................... 18 4.6 Global Status Register ............................... 19 4.7 Block Status Register ................................ 20 5.0 ELECTRICAL SPECIFICATIONS ................. 21 5.1 Absolute Maximum Ratings ....................... 21 5.2 Capacitance............................................... 22 5.3 Timing Nomenclature................................. 23 5.4 DC Characteristics (VCC = 3.3V 10%) ..... 26 5.5 DC Characteristics (VCC = 5.0V 10%, 5.0V 5%) ................ 29 3 28F016SA E REVISION HISTORY Description Original Version -- Added 56-Lead SSOP Package -- Separated AC Reading Timing Specs tAVEL, tAVGL for Extended Status Register Reads -- Modified Device Nomenclature -- Added Ordering Information -- Added Page Buffer Typical Program Performance numbers -- Added Typical Erase Suspend Latencies -- For ICCD (Deep Power-Down current) BYTE# must be at CMOS levels -- Added SSOP package mechanical specifications -- Revised document status from "Advanced Information" to "Preliminary" -- Section 5.11: Renamed specification "Erase Suspend Latency Time to Program" as "Auto Erase Suspend Latency Time to Program" -- Section 5.7: Added specifications t PHEL3, tPHEL5 -- TSOP dimension A1 = 0.05 mm (min) -- SSOP dimension B = 0.40 mm (max) -- Minor cosmetic changes Update: --Changed Deep Power Down Current -- Changed Standby Current -- Changed Sleep Mode Current Combined Commercial and Extended Temperature information into single datasheet Number -001 -002 -003 -004 4 E 1.0 1.1 28F016SA Internal algorithm automation allows word/byte programs and block erase operations to be executed using a two-write command sequence to the CUI in the same way as the 28F008SA 8-Mbit FlashFile memory. A superset of commands have been added to the basic 28F008SA command-set to achieve higher program performance and provide additional capabilities. These new commands and features include: * * * * * * Page Buffer Writes to Flash Command Queueing Capability Automatic Data Programs during Erase Software Locking of Memory Blocks Two-Byte Systems Successive Programs in 8-bit INTRODUCTION The documentation of the Intel 28F016SA memory device includes this datasheet, a detailed user's manual, and a number of application notes, all of which are referenced at the end of this datasheet. The datasheet is intended to give an overview of the chip feature-set and of the operating AC/DC specifications. The 16-Mbit Flash Product Family User's Manual provides complete descriptions of the user modes, system interface examples and detailed descriptions of all principles of operation. It also contains the full list of software algorithm flowcharts, and a brief section on compatibility with Intel 28F008SA. Product Overview The 28F016SA is a high-performance 16-Mbit (16,777,216 bit) block erasable nonvolatile random access memory organized as either 1 Mword x 16 or 2 Mbyte x 8. The 28F016SA includes thirtytwo 64-KB (65,536) blocks or thirty-two 32-KW (32,768) blocks. A chip memory map is shown in Figure 4. The implementation of a new architecture, with many enhanced features, will improve the device operating characteristics and results in greater product reliability and ease-of-use. Among the 28F016SA: * * * significant enhancements on the Erase All Unlocked Blocks Writing of memory data is performed in either byte or word increments typically within 6 s, a 33% improvement over the 28F008SA. A block erase operation erases one of the 32 blocks in typically 0.6 sec, independent of the other blocks, which is a 65% improvement over the 28F008SA. Each block can be written and erased a minimum of 100,000 cycles. Systems can achieve typically onemillion block erase cycles by providing wear-leveling algorithms and graceful block retirement. These techniques have already been employed in many flash file systems. Additionally, wear leveling of block erase cycles can be used to minimize the program/erase performance differences across blocks. The 28F016SA incorporates two Page Buffers of 256 bytes (128 words) each to allow page data writes. This feature can improve a system write performance by up to 4.8 times over previous flash memory devices. All operations are started by a sequence of command writes to the device. Three Status Registers (described in detail later) and a RY/BY# output pin provide information on the progress of the requested operation. While the 28F008SA requires an operation to complete before the next operation can be requested, the 28F016SA allows queueing of the next operation while the memory executes the current operation. This eliminates system overhead 5 3.3V Low Power Capability Improved Program Performance Dedicated Block Program/Erase Protection A 3/5# input pin reconfigures the device internally for optimized 3.3V or 5.0V read/program operation. The 28F016SA will be available in a 56-lead, 1.2 mm thick, 14 mm x 20 mm TSOP type I package or a 56-lead, 1.8 mm thick, 16 mm x 23.7 mm SSOP package. The TSOP form factor and pinout allow for very high board layout densities. SSOP packaging provides relaxed lead spacing dimensions. A Command User Interface (CUI) serves as the system interface between the microprocessor or microcontroller and the internal memory operation. 28F016SA when writing several bytes in a row to the array or erasing several blocks at the same time. The 28F016SA can also perform program operations to one block of memory while performing erase of another block. The 28F016SA provides user-selectable block locking to protect code or data such as device drivers, PCMCIA card information, ROM-executable O/S or application code. Each block has an associated nonvolatile lock-bit which determines the lock status of the block. In addition, the 28F016SA has a master Write Protect pin (WP#) which prevents any modifications to memory blocks whose lock-bits are set. The 28F016SA contains three types of Status Registers to accomplish various functions: * A Compatible Status Register (CSR) which is 100% compatible with the 28F008SA FlashFile memory's Status Register. This register, when used alone, provides a straightforward upgrade capability to the 28F016SA from a 28F008SAbased design. A Global Status Register (GSR) which informs the system of Command Queue status, Page Buffer status, and overall Write State Machine (WSM) status. 32 Block Status Registers (BSRs) which provide block-specific status information such as the block lock-bit status. two signals to enable or disable the entire chip. Both CE0# and CE1# must be active low to enable the device and, if either one becomes inactive, the chip will be disabled. This feature, along with the open drain RY/BY# pin, allows the system designer to reduce the number of control pins used in a large array of 16-Mbit devices. The BYTE# pin allows either x8 or x16 read/programs to the 28F016SA. BYTE# at logic low selects 8-bit mode with address A0 selecting between low byte and high byte. On the other hand, BYTE# at logic high enables 16-bit operation with address A1 becoming the lowest order address and address A0 is not used (don't care). A device block diagram is shown in Figure 1. The 28F016SA is specified for a maximum access time of 70 ns (tACC) at 5.0V operation (4.75V to 5.25V) over the commercial temperature range (0C to +70C). A corresponding maximum access time of 120 ns at 3.3V (3.0V to 3.6V and 0C to +70C) is achieved for reduced power consumption applications. The 28F016SA incorporates an Automatic Power Saving (APS) feature which substantially reduces the active current when the device is in the static mode of operation (addresses not switching). In APS mode, the typical ICC current is 1 mA at 5.0V (0.8 mA at 3.3V). A deep power-down mode of operation is invoked when the RP# (called PWD# on the 28F008SA) pin transitions low. This mode brings the device power consumption to less than 1.0 A, typically, and provides additional write protection by acting as a device reset pin during power transitions. A reset time is required from RP# switching high until outputs are again valid. In the deep power-down state, the WSM is reset (any current operation will abort) and the CSR, GSR and BSR registers are cleared. A CMOS standby mode of operation is enabled when either CE0# or CE1# transitions high and RP# stays high with all input control pins at CMOS levels. In this mode, the device typically draws an ICC standby current of 50 A. E * * The GSR and BSR memory maps for byte-wide and word-wide modes are shown in Figures 5 and 6. The 28F016SA incorporates an open drain RY/BY# output pin. This feature allows the user to OR-tie many RY/BY# pins together in a multiple memory configuration such as a Resident Flash Array. Other configurations of the RY/BY# pin are enabled via special CUI commands and are described in detail in the 16-Mbit Flash Product Family User's Manual. The 28F016SA also incorporates a dual chip-enable function with two input pins, CE0# and CE1#. These pins have exactly the same functionality as the regular chip-enable pin CE# on the 28F008SA. For minimum chip designs, CE1# may be tied to ground to use CE0# as the chip enable input. The 28F016SA uses the logical combination of these 6 2.0 DEVICE PINOUT The 28F016SA 56-lead TSOP Type I pinout configuration is shown in Figure 2. The 56-lead SSOP pinout configuration is shown in Figure 3. E DQ 28F016SA 8-15 DQ 0-7 Output Buffer Output Buffer Input Buffer Input Buffer 3/5# I/O Logic BYTE# Data Queue Registers ID Register Output Multiplexer CSR Page Buffers CE0# ESRs OE# CE1# CUI 0-20 A Data Comparator Input Buffer Y Decoder WE# WP# RP# Y Gating/Sensing 64-Kbyte Block 0 64-Kbyte Block 30 64-Kbyte Block 1 64-Kbyte Block 31 WSM Address Queue Latches RY/BY# X Decoder Program/Erase Voltage Switch VPP 3/5# VCC Address Counter GND 0489_01 Figure 1. 28F016SA Block Diagram Architectural Evolution Includes Page Buffers, Queue Registers and Extended Status Registers 7 28F016SA E Type INPUT Name and Function BYTE-SELECT ADDRESS: Selects between high and low byte when the device is in x8 mode. This address is latched in x8 data programs. Not used in x16 mode (i.e., the A 0 input buffer is turned off when BYTE# is high). WORD-SELECT ADDRESSES: Select a word within one 64-Kbyte block. A6-15 selects 1 of 1024 rows, and A 1-5 selects 16 of 512 columns. These addresses are latched during data programs. BLOCK-SELECT ADDRESSES: Select 1 of 32 erase blocks. These addresses are latched during data programs, block erase and lock block operations. INPUT INPUT INPUT/OUTPUT LOW-BYTE DATA BUS: Inputs data and commands during CUI write cycles. Outputs array, buffer, identifier or status data in the appropriate read mode. Floated when the chip is deselected or the outputs are disabled. INPUT/OUTPUT HIGH-BYTE DATA BUS: Inputs data during x16 data program operations. Outputs array, buffer or identifier data in the appropriate read mode; not used for Status Register reads. Floated when the chip is deselected or the outputs are disabled. INPUT CHIP ENABLE INPUTS: Activate the device's control logic, input buffers, decoders and sense amplifiers. With either CE0# or CE1# high, the device is deselected and power consumption reduces to standby levels upon completion of any current data program or block erase operations. Both CE0#, CE1# must be low to select the device. All timing specifications are the same for both signals. Device selection occurs with the latter falling edge of CE 0# or CE1#. The first rising edge of CE0# or CE1# disables the device. RESET/POWER-DOWN: RP# low places the device in a deep powerdown state. All circuits that burn static power, even those circuits enabled in standby mode, are turned off. When returning from deep power-down, a recovery time is required to allow these circuits to power-up. When RP# goes low, any current or pending WSM operation(s) are terminated, and the device is reset. All Status Registers return to ready (with all status flags cleared). OUTPUT ENABLE: Gates device data through the output buffers when low. The outputs float to tri-state off when OE# is high. NOTE: CEx# overrides OE#, and OE# overrides WE#. WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue Registers and Address Queue Latches. WE# is active low, and latches both address and data (command or array) on its rising edge. Page Buffer addresses are latched on the falling edge of WE#. 2.1 Lead Descriptions Symbol A0 A1-A15 A16-A20 DQ0-DQ7 DQ8-DQ15 CE0#,CE1# RP# INPUT OE# INPUT WE# INPUT 8 E Symbol RY/BY# WP# BYTE# 28F016SA 2.1 Lead Descriptions (Continued) Type OPEN DRAIN OUTPUT Name and Function READY/BUSY: Indicates status of the internal WSM. When low, it indicates that the WSM is busy performing an operation. RY/BY# high indicates that the WSM is ready for new operations (or WSM has completed all pending operations), or block erase is suspended, or the device is in deep power-down mode. This output is always active (i.e., not floated to tri-state off when OE# or CE0#,CE1# are high), except if a RY/BY# Pin Disable command is issued. WRITE PROTECT: Erase blocks can be locked by writing a nonvolatile lock-bit for each block. When WP# is low, those locked blocks as reflected by the Block-Lock Status bits (BSR.6), are protected from inadvertent data programs or block erases. When WP# is high, all blocks can be written or erased regardless of the state of the lock-bits. The WP# input buffer is disabled when RP# transitions low (deep power-down mode). BYTE ENABLE: BYTE# low places device in x8 mode. All data is then input or output on DQ0-7, and DQ8-15 float. Address A 0 selects between the high and low byte. BYTE# high places the device in x16 mode, and turns off the A0 input buffer. Address A1 then becomes the lowest order address. 3.3/5.0 VOLT SELECT: 3/5# high configures internal circuits for 3.3V operation. 3/5# low configures internal circuits for 5.0V operation. NOTES: Reading the array with 3/5# high in a 5.0V system could damage the device. There is a significant delay from 3/5# switching to valid data. VPP VCC GND NC SUPPLY SUPPLY SUPPLY ERASE/PROGRAM POWER SUPPLY: For erasing memory array blocks or writing words/bytes/pages into the flash array. DEVICE POWER SUPPLY (3.3V 10%, 5.0V 10%, 5.0V 5%): Do not leave any power pins floating. GROUND FOR ALL INTERNAL CIRCUITRY: Do not leave any ground pins floating. NO CONNECT: Lead may be driven or left floating. INPUT INPUT 3/5# INPUT 9 28F016SA E 28F016SV 28F032SA 28F032SA 28F016SV 3/5# CE1 # CE2 # A 20 A 19 A 18 A 17 A 16 VCC A 15 A 14 A 13 A 12 CE 0 # V PP RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 3/5# CE1 # NC A 20 A 19 A 18 A 17 A 16 VCC A 15 A 14 A 13 A 12 CE0 # V PP RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 3/5# CE1 # NC A 20 A 19 A 18 A 17 A 16 VCC A 15 A 14 A 13 A 12 CE 0 # V PP RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 E28F016SA 56-LEAD TSOP PINOUT 1.2 mm x 14 mm x 20 mm TOP VIEW 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 WP# WE# OE# RY/BY# DQ 15 DQ 7 DQ 14 DQ 6 GND DQ 13 DQ 5 DQ 12 DQ 4 V CC GND DQ 11 DQ 3 DQ 10 DQ 2 V CC DQ 9 DQ 1 DQ 8 DQ 0 A0 BYTE# NC NC WP# WE# OE# RY/BY# DQ 15 DQ 7 DQ 14 DQ 6 GND DQ 13 DQ 5 DQ 12 DQ 4 VCC GND DQ 11 DQ 3 DQ 10 DQ 2 VCC DQ 9 DQ 1 DQ 8 DQ 0 A0 BYTE# NC NC WP# WE# OE# RY/BY# DQ 15 DQ 7 DQ 14 DQ 6 GND DQ 13 DQ 5 DQ 12 DQ 4 V CC GND DQ 11 DQ 3 DQ 10 DQ 2 V CC DQ 9 DQ 1 DQ 8 DQ 0 A0 BYTE# NC NC 0489_02 NOTE: 56-Lead TSOP Mechanical Diagrams and Dimensions are shown at the end of this specification. Figure 2. TSOP Pinout Configuration 10 E 28F016SV CE 0# A12 A13 A14 A 15 3/5# CE1 # NC A20 A19 A 18 A17 A16 V CC GND DQ 6 DQ14 DQ 7 DQ15 RY/BY# OE# WE# WP# DQ 13 DQ 5 DQ 12 DQ 4 V CC CE 0 # A12 A 13 A14 A15 3/5# CE1 # NC A 20 A 19 A 18 A 17 A 16 V CC GND DQ 6 DQ14 DQ 7 DQ15 RY/BY# OE# WE# WP# DQ 13 DQ 5 DQ 12 DQ 4 V CC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1.8 mm x 16 mm x 23.7 mm TOP VIEW DA28F016SA 56-LEAD SSOP STANDARD PINOUT 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 V PP RP# A 11 A 10 A9 A1 A2 A3 A4 A5 A6 A7 A8 VCC DQ 9 DQ 1 DQ 8 DQ 0 A0 28F016SA 28F016SV V PP RP# A 11 A 10 A9 A1 A2 A3 A4 A5 A6 A7 GND A8 VCC DQ 9 DQ 1 DQ 8 DQ 0 A0 BYTE# NC NC DQ 2 DQ 10 DQ 3 DQ 11 GND 0489_17 GND BYTE# NC NC DQ 2 DQ 10 DQ 3 DQ 11 GND Figure 3. SSOP Pinout Configuration 11 28F016SA 3.0 MEMORY MAPS A[20-0] 1FFFFF 1F0000 1EFFFF 1E0000 1DFFFF 1D0000 1CFFFF 1C0000 1BFFFF 1B0000 1AFFFF 1A0000 19FFFF 190000 18FFFF 180000 17FFFF 170000 16FFFF 160000 15FFFF 150000 14FFFF 140000 13FFFF 130000 12FFFF 120000 11FFFF 110000 10FFFF 100000 0FFFFF 0F0000 0EFFFF 0E0000 0DFFFF 0D0000 0CFFFF 0C0000 0BFFFF 0B0000 0AFFFF 0A0000 09FFFF 090000 08FFFF 080000 07FFFF 070000 06FFFF 060000 05FFFF 050000 04FFFF 040000 03FFFF 030000 02FFFF 020000 01FFFF 010000 00FFFF 000000 E 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0489_03 Figure 4. 28F016SA Memory Map (Byte-Wide Mode) 12 E 3.1 x8 MODE 28F016SA Extended Status Register Memory Map A[20-0] RESERVED GSR RESERVED 1F0003H BSR 31 RESERVED RESERVED 1F0002H 1F0001H 1F0000H 1F0006H x16 MODE RESERVED A[20-1] F8003H GSR 1F0005H 1F0004H RESERVED BSR 31 F8001H RESERVED RESERVED F8002H . . . . . . F8000H 010002H 08001H RESERVED RESERVED 000006H RESERVED 000005H GSR 000004H RESERVED 000003H BSR 0 RESERVED RESERVED 000002H RESERVED BSR 0 GSR RESERVED 00003H 00002H RESERVED 00001H 000001H 000000H 0489_04 RESERVED 00000H 0489_05 Figure 5. Extended Status Register Memory Map (Byte-Wide Mode) Figure 6. Extended Status Register Memory Map (Word-Wide Mode) 13 28F016SA 4.0 4.1 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS Bus Operations for Word-Wide Mode (BYTE# = VIH) Mode Notes 1,2,7 1,6,7 1,6,7 RP# VIH VIH VIH CE1# VIL VIL VIL VIH VIH X VIL VIL VIL CE0# VIL VIL VIH VIL VIH X VIL VIL VIL OE# VIL VIH X WE# VIH VIH X A1 X X X DQ0-15 DOUT High Z High Z E RY/BY# X X X VOH VOH VOH X Read Output Disable Standby Deep Power-Down Manufacturer ID Device ID Write 1,3 4 4 1,5,6 VIL VIH VIH VIH X VIL VIL VIH X VIH VIH VIL X VIL VIH X High Z 0089H 66A0H DIN 4.2 Bus Operations for Byte-Wide Mode (BYTE# = VIL) Mode Notes 1,2,7 1,6,7 1,6,7 RP# VIH VIH VIH CE1# VIL VIL VIL VIH VIH X VIL VIL VIL CE0# VIL VIL VIH VIL VIH X VIL VIL VIL OE# VIL VIH X WE# VIH VIH X A0 X X X DQ0-7 DOUT High Z High Z RY/BY# X X X Read Output Disable Standby Deep Power-Down Manufacturer ID Device ID Write 1,3 4 4 1,5,6 VIL VIH VIH VIH X VIL VIL VIH X VIH VIH VIL X VIL VIH X High Z 89H A0H DIN VOH VOH VOH X NOTES: 1. X can be VIH or VIL for address or control pins except for RY/BY#, which is either VOL or VOH. 2. RY/BY# output is open drain. When the WSM is ready, block erase is suspended or the device is in deep power-down mode. RY/BY# will be at VOH if it is tied to VCC through a resistor. RY/BY# at VOH is independent of OE# while a WSM operation is in progress. 3. RP# at GND 0.2V ensures the lowest deep power-down current. 4. A0 and A1 at VIL provide manufacturer ID codes in x8 and x16 modes, respectively. A0 and A1 at VIH provide device ID codes in x8 and x16 modes, respectively. All other addresses are set to zero. 5. Commands for different block erase operations, data program operations or lock-block operations can only be successfully completed when VPP = VPPH. 6. While the WSM is running, RY/BY# in level-mode (default) stays at VOL until all operations are complete. RY/BY# goes to VOH when the WSM is not busy or in erase suspend mode. 7. RY/BY# may be at VOL while the WSM is busy performing various operations; for example, a Status Register read during a data program operation. 14 E 4.3 Read Array 28F016SA 28F008SA-Compatible Mode Command Bus Definitions First Bus Cycle Command Notes Oper Write 1 2 3 Write Write Write Write Write Write Write Addr X X X X X X X X Data(4) xxFFH xx90H xx70H xx50H xx40H xx10H xx20H xxB0H Write Write Write Write PA PA BA X PD PD xxD0H xxD0H Second Bus Cycle Oper Read Read Read Addr AA IA X Data AD ID CSRD Intelligent Identifier Read Compatible Status Register Clear Status Register Word/Byte Program Alternate Word/Byte Program Block Erase/Confirm Erase Suspend/Resume ADDRESS A = Array Address BA = Block Address IA = Identifier Address PA = Program Address X = Don't Care DATA AD = Array Data CSRD = CSR Data ID = Identifier Data PD = Program Data NOTES: 1. Following the Intelligent Identifier command, two read operations access the manufacturer and device signature codes. 2. The CSR is automatically available after device enters data program, block erase, or suspend operati ns. o 3. Clears CSR.3, CSR.4 and CSR.5. Also clears GSR.5 and all BSR.5 and BSR.2 bits. 4. The upper byte of the data bus (DQ8-15) during command writes is a "Don't Care" in x16 operation of the device. See Status Register definitions. 15 28F016SA 4.4 28F016SA-Performance Enhancement Command Bus Definitions First Bus Cycle Command Mode Notes 1 Oper Write Addr X Data(12) xx71H Second Bus Cycle Oper Read Addr RA Data(12) GSRD BSRD E Data X BCH X PA WCH BC(H,L) Third Bus Cycle Oper Addr Read Extended Status Register Page Buffer Swap Read Page Buffer Single Load to Page Buffer Sequential Load to Page Buffer x8 7 Write Write Write X X X xx72H xx75H xx74H Read Write PBA PBA PD PD 4,6,10 Write X xxE0H Write X BCL Write x16 Page Buffer Write to Flash x8 4,5,6,10 3,4,9,10 Write Write X X xxE0H xx0CH Write Write X A0 X A0 BA X WCL BC(L,H) Write Write x16 Two-Byte Program Lock Block/Confirm Upload Status Bits/Confirm Upload Device Information Erase All Unlocked Blocks/Confirm RY/BY# Enable to Level-Mode RY/BY# Pulse-OnWrite RY/BY# Pulse-OnErase RY/BY# Disable Sleep Abort x8 4,5,10 3 Write Write Write X X X X xx0CH xxFBH xx77H xx97H Write Write Write Write WCL WD(L,H) xxD0H xxD0H Write Write PA PA WCH WD(H,L) 2 Write Write X xx99H Write X xxD0H Write X xxA7H Write X xxD0H 8 Write X xx96H Write X xx01H 8 Write X xx96H Write X xx02H 8 Write X xx96H Write X xx03H 8 11 Write Write Write X X X xx96H xxF0H xx80H Write X xx04H ADDRESS BA = Block Address PBA = Page Buffer Address RA = Extended Register Address PA = Program Address X = Don't Care DATA AD = Array Data PD = Page Buffer Data BSRD = BSR Data GSRD = GSR Data WC (L,H) = Word Count (Low, High) BC (L,H) = Byte Count (Low, High) WD (L,H) = Write Data (Low, High) 16 NOTES: 1. RA can be the GSR address or any BSR address. See Figures 5 and 6 for Extended Status Register Memory Maps. 2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the actual lock-bit status. 3. A0 is automatically complemented to load the second byte of data. BYTE# must be at VIL. The A0 value determines which WD/BC is supplied first: A0 = 0 looks at the WDL/BCL, A0 = 1 looks at the WDH/BCH. 4. BCH/WCH must be at 00H for this product because of the 256-byte (128-word) Page Buffer size and to avoid writing the Page Buffer contents into more than one 256-byte segment within an array block. They are simply shown for future Page Buffer expandability. 5. In x16 mode, only the lower byte DQ0-7 is used for WCL and WCH. The upper byte DQ8-15 is a don't care. 6. PBA and PD (whose count is given in cycles 2 and 3) are supplied starting in the fourth cycle, which is not shown. 7. This command allows the user to swap between available Page Buffers (0 or 1). 8. These commands reconfigure the RY/BY# output to one of two pulse-modes or enable and disable the RY/BY# function. 9. Program address, PA, is the destination address in the flash array which must match the s ource address in the Page Buffer. Refer to the 16-Mbit Flash Product Family User's Manual. 10. BCL = 00H corresponds to a byte count of 1. Similarly, WCL = 00H corresponds to a word count of 1. 11. To ensure that the 28F016SA's power consumption during sleep mode reaches the deep power-down current level, the system also needs to de-select the chip by taking either or both CE0# or CE1# high. 12. The upper byte of the data bus (DQ8-15) during command writes is a "Don't Care" in x16 operation of the device. E 28F016SA 17 28F016SA 4.5 7 Compatible Status Register WSMS ESS 6 ES 5 DWS 4 VPPS 3 R 2 NOTES: R 1 E R 0 RY/BY# output or WSMS bit must be checked to determine completion of an operation (erase suspend, block erase or data program) before the appropriate Status bit (ESS, ES or DWS) is checked for success. If DWS and ES are set to "1" during a block erase attempt, an improper command sequence was entered. Clear the CSR and attempt the operation again. CSR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy CSR.6 = ERASE-SUSPEND STATUS 1 = Erase Suspended 0 = Erase In Progress/Completed CSR.5 = ERASE STATUS 1 = Error In Block Erasure 0 = Successful Block Erase CSR.4 = DATA WRITE STATUS 1 = Error in Data Program 0 = Data Program Successful CSR.3 = VPP STATUS 1 = VPP Low Detect, Operation Abort 0 = VPP OK The VPPS bit, unlike an A/D converter, does not provide continuous indication of VPP level. The WSM interrogates VPP's level only after the Data Program or Block Erase command sequences have been entered, and informs the system if VPP has not been switched on. VPPS is not guaranteed to report accurate feedback between VPPL and VPPH. CSR.2-0 = RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use; mask them out when polling the CSR. 18 E 4.6 WSMS 7 28F016SA Global Status Register OSS 6 DOS 5 DSS 4 QS 3 PBAS 2 NOTES: PBS 1 PBSS 0 GSR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy [1] RY/BY# output or WSMS bit must be checked to determine completion of an operation (block lock, erase suspend, any RY/BY# reconfiguration, Upload Status Bits, block erase or data program) before the appropriate Status bit (OSS or DOS) is checked for success. GSR.6 = OPERATION SUSPEND STATUS 1 = Operation Suspended 0 = Operation in Progress/Completed GSR.5 = DEVICE OPERATION STATUS 1 = Operation Unsuccessful 0 = Operation Successful or Currently Running GSR.4 = DEVICE SLEEP STATUS 1 = Device in Sleep 0 = Device Not in Sleep MATRIX 5/4 0 0 = Operation Successful or Currently Running 0 1 = Device in Sleep Mode or Pending Sleep 1 0 = Operation Unsuccessful 1 1 = Operation Unsuccessful or Aborted If operation currently running, then GSR.7 = 0. If device pending sleep, then GSR.7 = 0. Operation aborted: Unsuccessful due to Abort command. GSR.3 = QUEUE STATUS 1 = Queue Full 0 = Queue Available GSR.2 = PAGE BUFFER AVAILABLE STATUS 1 = One or Two Page Buffers Available 0 = No Page Buffer Available GSR.1 = PAGE BUFFER STATUS 1 = Selected Page Buffer Ready 0 = Selected Page Buffer Busy GSR.0 = PAGE BUFFER SELECT STATUS 1 = Page Buffer 1 Selected 0 = Page Buffer 0 Selected NOTE: 1. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block. GSR.7 provides indication when all queued operations are completed. The device contains two Page Buffers. Selected Page Buffer is currently busy with WSM operation. 19 28F016SA 4.7 BS 7 Block Status Register BLS 6 BOS 5 BOAS 4 QS 3 VPPS 2 NOTES: R 1 E R 0 [1] BSR.7 = BLOCK STATUS 1 = Ready 0 = Busy RY/BY# output or BS bit must be checked to determine completion of an operation (block lock, erase suspend, any RY/BY# reconfiguration, Upload Status Bits, block erase or data program) before the appropriate Status bits (BOS, BLS) is checked for success. BSR.6 = BLOCK-LOCK STATUS 1 = Block Unlocked for Program/Erase 0 = Block Locked for Program/Erase BSR.5 = BLOCK OPERATION STATUS 1 = Operation Unsuccessful 0 = Operation Successful or Currently Running BSR.4 = BLOCK OPERATION ABORT STATUS 1 = Operation Aborted 0 = Operation Not Aborted MATRIX 5/4 0 0 = Operation Successful or Currently Running 0 1 = Not a Valid Combination 1 0 = Operation Unsuccessful 1 1 = Operation Aborted The BOAS bit will not be set until BSR.7 = 1. Operation halted via Abort command. BSR.3 = QUEUE STATUS 1 = Queue Full 0 = Queue Available BSR.2 = VPP STATUS 1 = VPP Low Detect, Operation Abort 0 = VPP OK BSR.1-0 = RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use; mask them out when polling the BSRs. NOTE: 1. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block. GSR.7 provides indication when all queued operations are completed. 20 E 5.0 5.1 Sym TA VCC VPP V I IOUT 28F016SA NOTICE: This is a production datasheet. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings* Temperature under Bias .....................0C to +80C Storage Temperature....................-65C to +125C * WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may effect device reliability. VCC = 3.3V 10% Systems Parameter Operating Temperature, Commercial VCC with Respect to GND VPP Supply Voltage with Respect to GND Voltage on Any Pin (Except V CC, VPP) with Respect to GND Current into Any Non-Supply Pin Output Short Circuit Current Notes 1 2 2,3 2 5 4 Min 0 -0.2 -0.2 -0.5 Max 70 7.0 14.0 VCC +0.5 30 100 Units C V V V mA mA Test Conditions Ambient Temperature VCC = 5.0V 10% , VCC = 5.0V 5% Systems(6) Sym TA VCC VPP V I IOUT Parameter Operating Temperature, Commercial VCC with Respect to GND VPP Supply Voltage with Respect to GND Voltage on Any Pin (Except V CC, VPP) with Respect to GND Current into Any Non-Supply Pin Output Short Circuit Current Notes 1 2 2,3 2 5 4 Min 0 -0.2 -0.2 -2.0 Max 70 7.0 14.0 7.0 30 100 Units C V V V mA mA Test Conditions Ambient Temperature NOTES: 1. Operating temperature is for commercial product defined by this specification. 2. Minimum DC voltage is -10% on input/output pins. During transitions, this level may undershoot to -2.0V for periods <20 ns. Maximum DC voltage on input/output pins is VCC + 10% which, during transitions, may overshoot to VCC + 2.0V for periods <20 ns. 3. Maximum DC voltage on VPP may overshoot to +14.0V for periods <20 ns. 4. Output shorted for no more than one second. No more than one outpu shorted at a time. t 5. This specification also applies to pins marked "NC." 6. 5% VCC specifications refer to the 28F016SA-070 in its High Speed Test configuration. 21 28F016SA 5.2 Symbol CIN COUT CLOAD Capacitance Parameter Capacitance Looking into an Address/Control Pin Capacitance Looking into an Output Pin Load Capacitance Driven by Outputs for Timing Specifications Equivalent Testing Load Circuit Notes 1 1 1 Typ 6 8 Max 8 12 50 2.5 Units pF pF pF ns E Test Conditions TA = +25C, f = 1.0 MHz TA = +25C, f = 1.0 MHz For VCC = 3.3V 10% 50 Transmission Line Delay Notes 1 1 1 Typ 6 8 Max 8 12 100 30 Units pF pF pF pF ns ns Test Conditions TA = +25C, f = 1.0 MHz TA = +25C, f = 1.0 MHz For VCC = 5.0V 10% For VCC = 5.0V 5% 25 Transmission Line Delay 83 Transmission Line Delay For a 3.3V System: For a 5.0V System: Symbol CIN COUT CLOAD Parameter Capacitance Looking into an Address/Control Pin Capacitance Looking into an Output Pin Load Capacitance Driven by Outputs for Timing Specifications Equivalent Testing Load Circuit for VCC 10% Equivalent Testing Load Circuit for VCC 5% NOTE: 1. Sampled, not 100% tested. 2.5 2.5 22 E 5.3 tCE tOE tACC tAS tDH 28F016SA Timing Nomenclature All 3.3V system timings are measured from where signals cross 1.5V. For 5.0V systems use the standard JEDEC cross point definitions. Each timing parameter consists of five characters. Some common examples are defined below: tELQV time(t) from CE# (E) going low (L) to the outputs (Q) becoming valid (V) tGLQV time(t) from OE# (G) going low (L) to the outputs (Q) becoming valid (V) tAVQV time(t) from address (A) valid (V) to the outputs (Q) becoming valid (V) tAVWH time(t) from address (A) valid (V) to WE# (W) going high (H) tWHDX time(t) from WE# (W) going high (H) to when the data (D) can become undefined (X) Pin Characters A D Q E F G W P R V Y 5V 3V Address Inputs Data Inputs Data Outputs CE# (Chip Enable) BYTE# (Byte Enable) OE# (Output Enable) WE# (Write Enable) RP# (Deep Power-Down Pin) RY/BY# (Ready Busy) Any Voltage Level 3/5# Pin VCC at 4.5V Minimum VCC at 3.0V Minimum H L V X Z High Low Valid Pin States Driven, but not necessarily valid High Impedance 23 28F016SA E 2.0 INPUT TEST POINTS 0.8 0.8 0489_06 2.4 2.0 OUTPUT 0.45 AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0." Input timing begins at VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns. Figure 7. Transient Input/Output Reference Waveform (VCC = 5.0V 10%) for Standard Test Configuration(1) 3.0 INPUT 0.0 0489_07 1.5 TEST POINTS 1.5 OUTPUT AC test inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.5V. Input rise and fall times (10% to 90%) <10 ns. Figure 8. Transient Input/Output Reference Waveform (VCC = 3.3V 10%) High Speed Reference Waveform(2) (VCC = 5.0V 5%) NOTES: 1. Testing characteristics for 28F016SA-080/28F016SA-100. 2. Testing characteristics for 28F016SA-070/28F016SA-120/28F016SA-150. 24 E 2.5 ns of 25 Transmission Line From Output under Test Test Point 28F016SA Total Capacitance = 100 pF 0489_08 Figure 9. Transient Equivalent Testing Load Circuit (V CC = 5.0V 10%) 2.5 ns of 50 Transmission Line From Output under Test Test Point Total Capacitance = 50 pF 0489_09 Figure 10. Transient Equivalent Testing Load Circuit (V CC = 3.3V 10%) 2.5 ns of 83 Transmission Line From Output under Test Test Point Total Capacitance = 30 pF 0489_10 Figure 11. High Speed Transient Equivalent Testing Load Circuit (V CC = 5.0V 5%) 25 28F016SA 5.4 DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE E Vcc = 3.3V 10%, TA = 0C to +70C, -40C to +85C 3/5# = Pin Set High for 3.3V Operations Temp Sym IIL ILO ICCS Parameter Input Load Current Output Leakage Current VCC Standby Current Notes 1 1 1,5,6 50 Comm Typ Max 1 10 100 70 Extended Typ Max 1 10 250 Units A A A Test Conditions VCC = VCC Max VIN = VCC or GND VCC = VCC Max VIN = VCC or GND VCC = VCC Max CE0#, CE1#, RP#, = VCC 0.2V BYTE#, WP#, 3/5# = V CC 0.2V or GND 0.2V VCC = VCC Max CE0#, CE1#, RP# = VIH BYTE#, WP#, 3/5# = V IH or VIL RP# = GND 0.2V BYTE# = GND 0.2V or VCC 0.2V VCC = VCC Max CMOS: CE0#, CE1# = GND 0.2V, BYTE# = GND 0.2V or VCC 0.2V, Inputs = GND 0.2V or VCC 0.2V TTL: CE0#, CE1# = VIL, BYTE# = VIL or VIH, Inputs = VIL or VIH f = 8 MHz, I OUT = 0 mA VCC = VCC Max CMOS: CE0#, CE1# = GND 0.2V, BYTE# = GND 0.2V or VCC 0.2V, Inputs = GND 0.2V or VCC 0.2V TTL: CE0#, CE1# = VIL, BYTE# = VIL or VIH, Inputs = VIL or VIH f = 4 MHz, I OUT = 0 mA Program in Progress Block Erase in Progress CE0#, CE1# = VIH Block Erase Suspended 1 4 1 10 mA ICCD VCC Deep PowerDown Current VCC Read Current 1 1 5 3 35 A ICCR1 1,4,5 30 35 30 40 mA ICCR2 VCC Read Current 1,4,5 15 20 15 25 mA ICCW ICCE ICCES VCC Program Current for Word or Byte VCC Block Erase Current VCC Erase Suspend Current 1 1 1,2 8 6 3 12 12 6 8 6 3 12 12 6 mA mA mA 26 E 5.4 Sym IPPS IPPR IPPD 28F016SA DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE (Continued) Vcc = 3.3V 10%, TA = 0C to +70C, -40C to +85C 3/5# = Pin Set High for 3.3V Operations Temp Parameter VPP Standby/ Read Current VPP Deep PowerDown Current 1 Notes 1 Comm Typ 1 65 0.2 Max 10 200 5 Extended Typ 1 65 0.2 Max 10 200 5 Units A A A Test Conditions VPP VCC VPP > VCC RP# = GND 0.2V 27 28F016SA 5.4 DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE (Continued) E Vcc = 3.3V 10%, TA = 0C to +70C, -40C to +85C 3/5# = Pin Set High for 3.3V Operations Temp Sym IPPW IPPE IPPES VIL VIH Parameter VPP Program Current for Word or Byte VPP Block Erase Current VPP Erase Suspend Current Input Low Voltage Input High Voltage Notes 1 1 1 -0.3 2.0 Comm/Extended Min Typ 10 4 65 Max 15 10 200 0.8 VCC + 0.3 0.4 2.4 VCC -0.2 VPP during Normal Operations VPP during Program/ Erase Operations VCC Program/Erase Lock Voltage 3 3 0.0 11.4 2.0 12.0 6.5 12.6 Units mA mA A V V Test Conditions VPP = VPPH Program in Progress VPP = VPPH Block Erase in Progress VPP = VPPH Block Erase Suspended VOL VOH1 VOH2 VPPL VPPH VLKO Output Low Voltage Output High Voltage V V V V V V VCC = VCC Min IOL = 4 mA VCC = VCC Min IOH = -2.0 mA VCC = VCC Min IOH = -100 A NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 3.3V, VPP = 12.0V, T = 25C. These currents are valid for all product versions (package and speeds). 2. ICCES is specified with the device deselected. If the device is read while in erase suspend mode, current draw is the sum of ICCES and ICCR. 3. Block erases, word/byte programs and lock block operations are inhibited when VPP = VPPL and not guaranteed in the range between VPPH and VPPL. 4. Automatic Power Savings (APS) reduces ICCR to less than 1 mA in static operation. 5. CMOS Inputs are either VCC 0.2V or GND 0.2V. TTL Inputs are either VIL or VIH. 6. Standby current levels are not reached when putting the chip in standby mode immediately after reading the page buffer. Default the device into read array or read Status Register mode before entering standby to ensure standby current levels. 28 E 5.5 Sym IIL ILO ICCS 28F016SA DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE VCC = 5.0V 10%, 5.0V 5%, T A = 0C to +70C, -40C to +85C 3/5# Pin Set Low for 5V Operations Temp Parameter Input Load Current Output Leakage Current VCC Standby Current Notes 1 1 1,5,6 50 Comm Typ Max 1 10 100 70 Extended Typ Max 1 10 250 Units A A A Test Conditions VCC = VCC Max VIN = VCC or GND VCC = VCC Max VIN = VCC or GND VCC = VCC Max CE0#, CE1#, RP# = VCC 0.2V BYTE#, WP#, 3/5# = V CC 0.2V or GND 0.2V VCC = VCC Max CE0#, CE1#, RP# = VIH BYTE#, WP#, 3/5# = VIH or VIL RP# = GND 0.2V BYTE# = GND 0.2V or VCC 0.2V VCC = VCC Max CMOS: CE0#, CE1# = GND 0.2V, BYTE# = GND 0.2V or VCC 0.2V, Inputs = GND 0.2V or VCC 0.2V TTL: CE0#, CE1# = VIL, BYTE# = VIL or VIH, Inputs = VIL or VIH f = 10 MHz, I OUT = 0 mA VCC = VCC Max CMOS: CE0#, CE1# = GND 0.2V, BYTE# = GND 0.2V or VCC 0.2V, Inputs = GND 0.2V or VCC 0.2V TTL: CE0#, CE1# = VIL, BYTE# = VIL or VIH, Inputs = VIL or VIH f = 5 MHz, I OUT = 0 mA Program in Progress Block Erase in Progress CE0#, CE1# = VIH Block Erase Suspended 2 4 2 10 mA ICCD VCC Deep PowerDown Current VCC Read Current 1 1 5 10 60 A ICCR1 1,4,5 50 60 55 70 mA ICCR2 VCC Read Current 1,4,5 30 35 30 35 mA ICCW ICCE ICCES VCC Program Current for Word or Byte VCC Block Erase Current VCC Erase Suspend Current 1 1 1,2 25 18 5 35 25 10 25 18 5 35 25 10 mA mA mA 29 28F016SA 5.5 DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE E (Continued) VCC = 5.0V 10%, 5.0V 5%, T A = 0C to +70C, -40C to +85C 3/5# Pin Set Low for 5V Operations Temp Sym IPPS IPPR IPPD Parameter VPP Standby/Read Current VPP Deep PowerDown Current 1 Notes 1 Comm Typ 1 65 0.2 Max 10 200 5 Extended Typ 1 65 0.2 Max 10 200 5 Units A A A Test Conditions VPP VCC VPP > VCC RP# = GND 0.2V 30 E 5.5 DC Sym IPPW IPPE IPPES VIL VIH VOL VOH1 VOH2 VPPL VPPH VLKO 28F016SA Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE (Continued) VCC = 5.0V 10%, 5.0V 5%,T A = 0C to +70C, -40C to +85C 3/5# Pin Set Low for 5V Operations Temp Parameter VPP Program Current for Word or Byte VPP Block Erase Current VPP Erase Suspend Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 0.85 VCC VCC VPP during Normal Operations VPP during Program/ Erase Operations VCC Program/Erase Lock Voltage 3 -0.4 0.0 11.4 2.0 12.0 6.5 12.6 Notes 1 1 1 -0.5 2.0 Comm/Extended Min Typ 7 5 65 Max 12 10 200 0.8 VCC +0.5 0.45 Units mA mA A V V V V V V V V VCC = VCC Min IOL = 5.8 mA VCC = VCC Min IOH = -2.5 mA VCC = VCC Min IOH = -100 A Test Conditions VPP = VPPH Program in Progress VPP = VPPH Block Erase in Progress VPP = VPPH Block Erase Suspended NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0V, VPP = 12.0V, T = 25C. These currents are valid for all product versions (package and speeds). 2. ICCES is specified with the device deselected. If the device is read while in erase suspend mode, current draw is the sum of ICCES and ICCR. 3. Block erases, word/byte programs and lock block operations are inhibited when VPP = VPPL and not guaranteed in the range between VPPH and VPPL. 4. Automatic Power Saving (APS) reduces ICCR to less than 2 mA in static operation. 5. CMOS Inputs are either VCC 0.2V or GND 0.2V. TTL Inputs are either VIL or VIH. 6. Standby current levels are not reached when putting the chip in standby mode immediat ly after reading the page buffer. e Default the device into read array or read Status Register mode before entering standby to ensure standby current levels. 31 28F016SA 5.6 AC Characteristics-Read Only Operations: COMMERCIAL AND EXTENDED TEMPERATURE(1) Temp Speed Commercial -120 -150 3.3V 10% 50 pF Min 120 120 2 120 620 2 3 3 3 3 3 0 0 15 0 0 30 0 20 0 45 0 35 0 Max Min 150 150 150 750 50 0 Max Min 150 E Extended -150 Units Max ns 150 150 750 50 ns ns ns ns ns 35 ns ns 20 ns ns VCC = 3.3V 10%, T A = 0C to +70C, -40C to +85C Sym Parameter VCC Load Notes tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tOH Read Cycle Time Address to Output Delay CE# to Output Delay RP# High to Output Delay OE# to Output Delay CE# to Output in Low Z CE# to Output in High Z OE# to Output in Low Z OE# to Output in High Z Output Hold from Address, CE# or OE# Change, Whichever Occurs First BYTE# to Output Delay BYTE# Low to Output in High Z CE# Low to BYTE# High or Low tFLQV tFHQV tFLQZ tELFL tELFH 3 3 3 120 30 5 150 40 5 150 40 5 ns ns ns For Extended Status Register Reads Temp Speed Symbol Parameter VCC Load Notes tAVEL tAVGL 32 Address Setup to CE# Going Low Address Setup to OE# Going Low 3,4 3,4 Min 0 0 Commercial -120 3.3V 10% 50 pF Max Min 0 0 Max ns ns Extended -150 Units E 5.6 Sym tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tOH 28F016SA AC Characteristics-Read Only Operations: COMMERCIAL AND EXTENDED TEMPERATURE(1) (Continued) Temp Speed Parameter VCC Load Notes Read Cycle Time Address to Output Delay CE# to Output Delay RP# to Output Delay OE# to Output Delay CE# to Output in Low Z CE# to Output in High Z OE# to Output in Low Z OE# to Output in High Z Output Hold from Address, CE# or OE# Change, Whichever Occurs First BYTE# to Output Delay BYTE# Low to Output in High Z CE# Low to BYTE# High or Low 2 3 3 3 3 3 0 0 15 0 0 25 0 15 0 2 -70 5.0V 5%V 30 pF Min 70 70 70 400 30 0 30 0 15 Max Commercial -80 5.0V 10%V 50 pF Min 80 80 80 480 35 0 30 Max Min 100 100 100 550 40 Comm/Ext -100 5.0V 10%V 50% Max ns ns ns ns ns ns ns ns ns ns Units VCC = 5.0V 10%, 5.0V 5%, T A = 0C to +70C. -40C to +85C tFLQV tFHQV tFLQZ tELFL tELFH 3 3 3 70 25 5 80 30 5 100 30 5 ns ns ns 33 28F016SA For Extended Status Register Reads Temp Load Versions(5) VCC 5% VCC 10% Sym tAVEL Parameter Address Setup to CE# Going Low Address Setup to OE# Going Low Notes 3,4 Min 0 Max Commercial 30 pF 28F016SA-070(6) 28F016SA-080(7) Min 0 Max Commercial 50 pF E Comm/Ext 50 pF Units 28F016SA-100(7) Min 0 Max ns 0 0 ns tAVGL 3,4 0 NOTES: 1. See AC Input/Output Reference Waveforms for timing measurements, Figures 7 and 8. 2. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. 3. Sampled, not 100% tested. 4. This timing parameter is used to latch the correct BSR data onto the outputs. 5. Device speeds are defined as: 70/80 ns at VCC = 5.0V equivalent to 120 ns at VCC = 3.3V 100 ns at VCC = 5.0V equivalent to 150 ns at VCC = 3.3V 6. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for High Speed Test Configuration. 7. See Standard AC Input/Output Reference Waveforms and AC Testing Load Circuit. 34 E V IH ADDRESSES (A) VIL t AVAV V IH 28F016SA ADDRESSES STABLE CEx# (E)(1) V IL t AVEL t EHQZ VIH t AVGL OE# (G) V IL t GHQZ VIH WE# (W) V IL t GLQV t ELQV t GLQX tELQX t OH VOH DATA (D/Q) V OL HIGH Z VALID OUTPUT HIGH Z t AVQV 5.0V V CC GND t VIH RP# (P) V IL 0489_11 PHQV NOTE: 1. CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high. Figure 12. Read Timing Waveforms 35 28F016SA E ADDRESSES STABLE t AVAV t AVFL = t ELFL VIH ADDRESSES (A) V IL VIH CEx #(E) (1) V IL t EHQZ VIH OE# (G) V IL t AVEL t GHQZ t ELFL t AVGL t FLQV = t AVQV BYTE# (F) V IL t GLQV t ELQV t GLQX VOH t OH VIH t ELQX HIGH Z DATA OUTPUT t AVQV DATA OUTPUT DATA (DQ0-DQ7) VOL VOH HIGH Z t FLQZ DATA OUTPUT HIGH Z DATA (DQ8-DQ15) VOL HIGH Z 0489_12 NOTE: 1. CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high. Figure 13. BYTE# Timing Waveforms 36 E 5.7 RP# (P) 28F016SA Power-Up and Reset Timings: COMMERCIAL/EXTENDED TEMPERATURE VCC Power-Up t YHPH t YLPH 3/5# (Y) 5.0V t PLYL 3.3V 4.5V VCC 0V (3V,5V) t PL5V CE X # t PHEL3 Address (A) Valid t PHEL5 Valid t AVQV Data (Q) Valid 3.3V Outputs t AVQV Valid 5.0V Outputs t PHQV t PHQV 0489_13 Figure 14. VCC Power-Up and RP# Reset Waveforms Symbol tPLYL tPLYH tYLPH tYHPH tPL5V tPL3V tPHEL3 tPHEL5 tAVQV tPHQV Parameter RP# Low to 3/5# Low (High) 3/5# Low (High) to RP# High RP# Low to VCC at 4.5V minimum (to VCC at 3.0V min or 3.6V max) RP# High to CE# Low (3.3V VCC) RP# High to CE# Low (5V VCC) Address Valid to Data Valid for V CC = 5V 10% RP# High to Data Valid for VCC = 5V 10% 1 2 1 1 3 3 Notes Min 0 2 0 500 330 80 480 Max Unit s s s ns ns ns ns NOTES: CE0#, CE1# and OE# are switched low after Power-Up. 1. The tYLPH/tYHPH and tPHEL3/tPHEL5 times must be strictly followed to guarantee all other read and program specifications. 2. The power supply may start to switch concurrently with RP# going low. 3. The address access time and RP# high to data valid time are shown for 5V VCC operation of the 28F016SA-080. Refer to the AC Characteristics Read Only Operations for 3.3V VCC and all other speed options. 37 28F016SA 5.8 AC Characteristics for WE#-Controlled Command Write Operations: COMMERCIAL AND EXTENDED TEMPERATURE(1) Temp Commercial Min 120 3 100 480 10 2,6 2,6 75 75 75 2 2 10 10 10 45 0 100 3 0 0 Typ Max Comm/Extended Min 150 100 480 10 75 75 75 10 10 10 75 0 100 Typ Max E Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns VCC = 3.3V 10%, T A = 0C to +70C, -40C to +85C Sym tAVAV tVPWH tPHEL tELWL tAVWH tDVWH tWLWH tWHDX tWHAX tWHEH tWHWL tGHWL tWHRL tRHPL Parameter Write Cycle Time VPP Setup to WE# Going High RP# Setup to CE# Going Low CE# Setup to WE# Going Low Address Setup to WE# Going High Data Setup to WE# Going High WE# Pulse Width Data Hold from WE# High Address Hold from WE# High CE# Hold from WE# High WE# Pulse Width High Read Recovery before Write WE# High to RY/BY# Going Low RP# Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High RP# High Recovery to WE# Going Low Write Recovery before Read VPP Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High Duration of Word/Byte Program Operation Duration of Block Erase Operation Notes tPHWL tWHGL tQVVL 1 95 0 1 120 0 s ns s tWHQV1 tWHQV2 4,5 4 5 0.3 9 Note 7 10 5 0.3 9 Note 7 10 s sec 38 E 5.8 Sym tAVAV tVPWH tPHEL 28F016SA AC Characteristics for WE#-Controlled Command Write Operations: COMMERCIAL AND EXTENDED TEMPERATURE(1) (Continued) VCC = 5.0V 10%, 5.0V 5%, T A = 0C to +70C, -40C to +85C Temp Versions VCC 5% VCC 10% Parameter Write Cycle Time VPP Setup to WE# Going High RP# Setup to CE# Going Low CE# Setup to WE# Going Low Address Setup to WE# Going High Data Setup to WE# Going High WE# Pulse Width Data Hold from WE# High Address Hold from WE# High CE# Hold from WE# High WE# Pulse Width High Read Recovery before Write 2 2,6 3 Notes Min 70 100 Typ Max Commercial 28F016SA-070 28F016SA-080 Min 80 100 Typ Max 28F016SA-100 Min 100 100 Typ Max ns ns Commercial Comm/Ext Unit 480 480 480 ns tELWL 0 0 0 ns tAVWH 50 50 50 ns tDVWH 2,6 50 50 50 ns tWLWH tWHDX 40 0 50 0 50 0 ns ns tWHAX 2 10 10 10 ns tWHEH tWHWL tGHWL 10 30 0 10 30 0 10 50 0 ns ns ns 39 28F016SA 5.8 AC Characteristics for WE#-Controlled Command Write Operations: COMMERCIAL AND EXTENDED TEMPERATURE(1) (Continued) E Unit Max 100 ns ns VCC = 5.0V 10%, 5.0V 5%, T A = 0C to +70C, -40C to +85C Temp Versions VCC 5% VCC 10% Sym tWHRL Parameter WE# High to RY/BY# Going Low RP# Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High RP# High Recovery to WE# Going Low Write Recovery before Read VPP Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High 4,5 3 0 Notes Min Typ Max 100 Commercial 28F016SA-070 28F016SA-080 Min Typ Max 100 28F016SA-100 Min Typ Commercial Comm/Ext tRHPL 0 0 tPHWL 1 1 1 s tWHGL 60 65 80 ns tQVVL 0 0 0 s tWHQV1 Duration of Word/Byte Program Operation tWHQV2 Duration of Block Erase Operation 4.5 6 Note 7 4.5 6 Note 7 4.5 6 Note 7 s 4 0.3 10 0.3 10 0.3 10 sec 40 NOTES: CE# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high. 1. Read timings during data program and block erase are the same as for normal read. 2. Refer to command definition tables for valid address and data values. 3. Sampled, but not 100% tested. 4. Data program/block erase durations are measured to valid Status Register data. 5. Word/byte program operations are typically performed with 1 programming pulse. 6. Address and data are latched on the rising edge of WE# for all command write operations. 7. This information will be available in a technical paper. Please call Intel's Application Hotline or your local Intel sales office for more information. E DEEP POWER-DOWN IH ADDRESSES (A) V NOTE 1 IL V IH ADDRESSES (A) V NOTE 2 IL V 28F016SA WRITE DATA-WRITE OR ERASE SETUP COMMAND WRITE VALID ADDRESS & DATA (DATA-WRITE) OR ERASE CONFIRM COMMAND A AUTOMATED DATA-WRITE OR ERASE DELAY WRITE READ EXTENDED REGISTER COMMAND READ EXTENDED STATUS REGISTER DATA IN t WHAX A=RA t AVAV t AVWH READ COMPATIBLE STATUS REGISTER DATA NOTE 3 A t IN t WHAX t AVAV AVWH V CEx # (E) NOTE 4 IH IL t ELWL t WHEH t WHGL V V OE# (G) V IH IL t WHWL t WHQV1,2 t GHWL V WE# (W) V IH IL t t DVWH D WLWH t WHDX V DATA (D/Q) IH IL HIGH Z t PHWL V IN D IN D IN D OUT D IN t V RY/BY# (R) V OH OL WHRL t V RP# (P) V RHPL NOTE 5 IH IL t V V V PP (V) V PPH VPWH t QVVL PPL IN V IL 0489_14 NOTES: 1. This address string depicts data program/block erase cycles with corresponding verification vi ESRD. a 2. This address string depicts data program/block erase cycles with corresponding verification via CSRD. 3. This cycle is invalid when using CSRD for verification during data program/block erase operations. 4. CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high. 5. RP# low transition is only to show tRHPL; not valid for above read and program cycles. Figure 15. AC Waveforms for Command Write Operations 41 28F016SA 5.9 AC Characteristics for CE#-Controlled Command Write Operations: COMMERCIAL AND EXTENDED TEMPERATURE(1) Temp Commercial -120 Min 120 3 100 480 0 2,6 2,6 75 75 75 2 2 10 10 10 45 0 100 3 0 0 Typ Max Min 150 100 480 0 75 75 75 10 10 10 75 0 100 Comm/Ext -150 Typ Max E Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns VCC = 3.3V 10%, TA = 0C to +70C, -40C to +85C Sym Parameter Speed Notes tAVAV tVPEH tPHWL tWLEL tAVEH tDVEH tELEH tEHDX tEHAX tEHWH tEHEL tGHEL tEHRL tRHPL Write Cycle Time VPP Setup to CE# Going High RP# Setup to WE# Going Low WE# Setup to CE# Going Low Address Setup to CE# Going High Data Setup to CE# Going High CE# Pulse Width Data Hold from CE# High Address Hold from CE# High WE Hold from CE# High CE# Pulse Width High Read Recovery before Write CE# High to RY/BY# Going Low RP# Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High RP# High Recovery to CE# Going Low Write Recovery before Read VPP Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High Duration of Word/Byte Program Operation Duration of Block Erase Operation 4,5 4 tPHEL tEHGL tQVVL 1 95 0 1 120 0 s ns s tEHQV1 tEHQV2 5 0.3 9 Note 7 10 5 0.3 9 Note 7 10 s sec 42 E 5.9 Sym tAVAV tVPEH tPHWL 28F016SA AC Characteristics for CE#-Controlled Command Write Operations: COMMERCIAL AND EXTENDED TEMPERATURE(1) (Continued) Temp Versions VCC 5% VCC 10% Parameter Write Cycle Time VPP Setup to CE# Going High RP# Setup to WE# Going Low WE# Setup to CE# Going Low Address Setup to CE# Going High Data Setup to CE# Going High CE# Pulse Width Data Hold from CE# High Address Hold from CE# High WE# Hold from CE# High CE# Pulse Width High Read Recovery before Write CE# High to RY/BY# Going Low 2 2 2,6 3 Notes Min 70 100 Typ Max Commercial 28F016SA-070 28F016SA-080 Min 80 100 Typ Max 28F016SA-100 Min 100 100 Typ Max ns ns Commercial Comm/Ext Unit VCC = 5.0 to 10% , 5.0 5%, T A = 0C to +70C, -40C to +85C 3 480 480 480 ns tWLEL tAVEH 0 50 0 50 0 50 ns ns tDVEH 2,6 50 50 50 ns tELEH tEHDX tEHAX tEHWH tEHEL tGHEL tEHRL 40 0 10 10 30 0 100 50 0 10 10 30 0 100 50 0 10 10 50 0 100 ns ns ns ns ns ns ns 43 28F016SA 5.9 AC Characteristics for CE#-Controlled Command Write Operations: COMMERCIAL AND EXTENDED TEMPERATURE(1) (Continued) Temp Versions VCC 5% VCC 10% Commercial 28F016SA-070 28F016SA-080 Min 0 Typ Max Min 0 Typ Max Commercial Comm/Ext E Unit Max ns s VCC = 5.0 to 10%, 5.0V 5%, T A = 0C to +70C, -40C to +85C 28F016SA-100 Min 0 Typ Sym tRHPL Parameter RP# Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High RP# High Recovery to CE# Going Low Write Recovery before Read VPP Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High Notes 3 tPHEL 1 1 1 tEHGL tQVVL 60 0 65 0 80 0 s s tEHQV1 Duration of Word/Byte Program Operation tEHQV2 Duration of Block Erase Operation 4,5 4.5 6 Note 7 4.5 6 Note 7 4.5 6 Note 7 s 4 0.3 10 0.3 10 0.3 10 sec NOTES: CE# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high. 1. Read timings during data program and block erase are the same as for normal read. 2. Refer to command definition tables for valid address and data values. 3. Sampled, but not 100% tested. 4. Data program/block erase durations are measured to valid Status Register data. 5. Word/byte program operations are typically performed with 1 programming pulse. 6. Address and data are latched on the rising edge of CE# for all command write operations. 7. This information will be available in a technical paper. Please call Intel's Application Hotline or your local Intel sales office for more information. 44 E DEEP POWER-DOWN IH ADDRESSES (A) V IL NOTE 1 t AVAV t V WRITE DATA-WRITE OR ERASE SETUP COMMAND WRITE VALID ADDRESS & DATA (DATA-WRITE) OR ERASE CONFIRM COMMAND A AUTOMATED DATA-WRITE OR ERASE DELAY WRITE READ EXTENDED REGISTER COMMAND READ EXTENDED STATUS REGISTER DATA IN t EHAX A=RA AVEH READ COMPATIBLE STATUS REGISTER DATA NOTE 3 V IH ADDRESSES (A) V NOTE 2 IL 28F016SA A t t IN t EHAX AVAV AVEH V WE# (W) V IH IL t WLEL t EHWH t EHGL V OE# (G) V IH IL t EHEL t EHQV1,2 t GHEL V CEx#(E) V NOTE 4 IH IL t t DVEH D ELEH t EHDX D V DATA (D/Q) IH IL HIGH Z t PHEL V IN IN D IN D OUT D IN t V RY/BY# (R) V OH OL EHRL t V RP# (P) V RHPL NOTE 5 IH IL t V V (V) V PP V V PPH PPL VPEH t QVVL IH IL 0489_15 NOTES: 1. This address string depicts data program/block erase cycles with corresponding verification via ESRD. 2. This address string depicts data program/block erase cycles with corresponding verification via CSRD. 3. This cycle is invalid when using CSRD for verification during data program/block erase operations. 4. CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high. 5. RP# low transition is only to show tRHPL; not valid for above read and program cycles. Figure 16. Alternate AC Waveforms for Command Write Operations 45 28F016SA 5.10 AC Characteristics for Page Buffer Write Operations: COMMERCIAL AND EXTENDED TEMPERATURE(1) Temp Commercial -120 Min 120 10 3 2 0 75 75 2 2 10 10 10 45 0 95 Typ Max Min 150 10 0 75 75 10 10 10 75 0 120 E Comm/Ext -150 Typ Max ns ns ns ns ns ns ns ns ns ns ns Unit VCC = 3.3V 10%, T A = 0C to +70C, -40C to +85C Sym tAVAV tELWL tAVWL tDVWH tWLWH tWHDX tWHAX tWHEH tWHWL tGHWL tWHGL Parameter Write Cycle Time CE# Setup to WE# Going Low Address Setup to WE# Going Low Data Setup to WE# Going High WE# Pulse Width Data Hold from WE# High Address Hold from WE# High CE# Hold from WE# High WE# Pulse Width High Read Recovery before Write Write Recovery before Read Speed Notes 46 E Sym tAVAV tELWL tAVWL tDVWH tWLWH tWHDX tWHAX tWHEH tWHWL tGHWL tWHGL 28F016SA 5.10 AC Characteristics for Page Buffer Write Operations: COMMERCIAL AND EXTENDED TEMPERATURE(1) (Continued) VCC = 5.0V 10%, 5.0V 5%, T A = 0C to +70C, -40C to +85C Temp Parameter Speed VCC Notes Write Cycle Time CE# Setup to WE# Going Low Address Setup to WE# Going Low Data Setup to WE# Going High WE# Pulse Width Data Hold from WE# High Address Hold from WE# High CE# Hold from WE# High WE# Pulse Width High Read Recovery before Write Write Recovery before Read 2 2 3 2 Commercial -70 5.0V 5% Min 70 0 0 50 40 0 10 10 30 0 60 Typ Max Commercial -80 5.0V 10% Min 80 0 0 50 50 0 10 10 30 0 65 Typ Max Comm/Ext -100 5.0V 10% Min 100 0 0 50 50 0 10 10 50 0 80 Typ Max ns ns ns ns ns ns ns ns ns ns ns Unit NOTES: CE# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high. 1. These are WE#-controlled write timings, equivalent CE#-controlled write timings apply. 2. Sampled, but not 100% tested. 3. Address must be valid during the entire WE# low pulse or the entire CE# low pulse for CE#-controlled writes. 47 28F016SA E t WHEH t ELWL t WHWL t AVWL t WLWH t WHAX V CEx#(E) V IH IL V WE# (W) V IH IL V IH ADDRESSES (A) V IL VALID t DVWH V DATA (D/Q) V IL t WHDX IH HIGH Z DIN 0489_16 Figure 17. Page Buffer Write Timing Waveforms (Loading Data to the Page Buffer) 48 E 5.11 Sym tWHRH1 tWHRH2 tWHRH3 28F016SA Erase and Word/Byte Write Performance, Cycling Performance and Suspend Latency(3) Parameter Page Buffer Byte Write Time Page Buffer Word Write Time Word/Byte Program Time Block Program Time Block Program Time Block Erase Time Full Chip Erase Time Erase Suspend Latency Time to Read Auto Erase Suspend Latency Time to Write Erase Cycles 5 Notes 2,4 2,4 2 2 2 2 2 Min Typ(1) 3.26 6.53 9 0.6 0.3 0.8 25.6 7.0 10.0 100,000 1,000,000 Max Note 6 Note 6 Note 6 2.1 1.0 10 Units s s s sec sec sec sec s s Cycles Byte Prog. Mode Word Prog. Mode Test Conditions VCC = 3.3V 10%, VPP = 12.0V 0.6V, T A = 0C to +70C VCC = 5.0V 10%, V PP = 12.0V 0.6V, T A = 0C to +70C Sym Parameter Page Buffer Byte Write Time Page Buffer Word Write Time tWHRH1 tWHRH2 tWHRH3 Word/Byte Program Time Block Program Time Block Program Time Block Erase Time Full Chip Erase Time Erase Suspend Latency Time to Read Auto Erase Suspend Latency Time to Write Erase Cycles 5 Notes 2,4 2,4 2 2 2 2 2 Min Typ(1) 2.76 5.51 6 0.4 0.2 0.6 19.2 5.0 8.0 100,000 1,000,000 Max Note 6 Note 6 Note 6 2.1 1.0 10 Units s s s sec sec sec sec s s Cycles Byte Prog. Mode Word Prog. Mode Test Conditions NOTES: 1. +25C, VCC = 3.3V or 5.0V nominal, VPP = 12.0V nominal, 10K cycles. 2. Excludes system-level overhead. 3. These performance numbers are valid for all speed versions. 4. This assumes using the full Page Buffer to data program to the flash memory (256 bytes or 128 words). 5. Typical 1,000,000 cycle performance assumes the application uses block retirement techniques. 6. This information will be available in a technical paper. Please call Intel's Application Hotline or your local Intel Sales office for more information. 49 28F016SA 6.0 DERATING CURVES E 290489-16.eps 290489-19.eps Figure 18. ICC vs. Frequency (VCC = 5.5V) for x8 or x16 Operation Figure 20. ICC vs. Frequency (VCC = 3.6V) for x8 or x16 Operation 290489-18.eps 290489-21.eps Figure 19. ICC during Block Erase 50 Figure 21. IPP during Block Erase E 28F016SA 290489-24.eps Figure 22. Access Time (tACC) vs. Output Loading 290489-25.eps 290489-26 Figure 23. IPP during Word Write Operation Figure 24. IPP during Page Buffer Write Operation 51 28F016SA 7.0 MECHANICAL SPECIFICATIONS FOR TSOP E 290489-28.eps Figure 25. Mechanical Specifications of the 28F016SA 56-Lead TSOP Type 1 Package Family: Thin Small Outline Package Symbol Minimum A A1 A2 b c D1 E e D L N Y Z 52 0.150 0.250 0 19.80 0.500 0.05 0.965 0.100 0.115 18.20 13.80 0.995 0.150 0.125 18.40 14.00 0.50 20.00 0.600 56 3 5 0.100 0.350 20.20 0.700 1.025 0.200 0.135 18.60 14.20 Nominal Millimeters Maximum 1.20 Notes E 8.0 28F016SA MECHANICAL SPECIFICATIONS FOR SSOP a E He A2 b R2 L1 Detail A D R1 A B e 1 Y C A1 See Detail A 0528_20 Figure 26. Mechanical Specifications of the 56-Lead SSOP Package Family: Shrink Small Outline Package Symbol Minimum A A1 A2 B C D E e1 He N L1 Y a b R1 R2 2 3 0.15 0.15 3 3 0.20 0.20 0.45 15.70 0.47 1.18 0.25 0.13 23.40 13.10 Nominal 1.80 0.52 1.28 0.30 0.15 23.70 13.30 0.80 16.00 56 0.50 0.55 0.10 4 5 0.25 0.25 53 16.30 Millimeters Maximum 1.90 0.57 1.38 0.40 0.20 24.00 13.50 Notes 28F016SA APPENDIX A DEVICE NOMENCLATURE AND ORDERING INFORMATION E DA 2 8 F 0 1 6SA - 0 7 0 ACCESS SPEED DA = Commercial Temperature 56-Lead SSOP E = Commercial Temperature 56-Lead TSOP T = Extended Temperature 56-Lead SSOP 70 ns 100 ns 100 ns 0489_18 Valid Combinations Option 1 2 3 4 5 Order Code E28F016SA-070 E28F016SA-100 DA28F016SA-070 DA28F016SA-100 DT28F016SA-100 VCC = 3.3V 10%, 50 pF Load E28F016SA-120 E28F016SA-150 DA28F016SA-120 DA28F016SA-150 DT28F016SA-150 VCC = 5.0V 10%, 100 pF Load E28F016SA-080 E28F016SA-100 DA28F016SA-080 DA28F016SA-100 DT28F016SA-150 DT28F016SA-150 DA28F016SA-070 VCC = 5.0V 5%, 30 pF Load E28F016SA-070 54 E Order Number 297372 290490 290528 290429 292092 292123 292126 292144 292159 294016 297534 297508 28F016SA APPENDIX B ADDITIONAL INFORMATION(1,2) Document/Tool 16-Mbit Flash Product Family User's Manual DD28F032SA 32-Mbit FlashFileTM Memory Datasheet 28F016SV FlashFileTM Memory Datasheet 28F008SA 8-Mbit FlashFileTM Memory Datasheet AP-357 Power Supply Solutions for Flash Memory AP-374 Flash Memory Write Protection Techniques AP-377 16-Mbit Flash Product Family Software Drivers 28F016SA, 28F016SV, 28F016XS, 28F016XD AP-393 28F016SV Compatibility with 28F016SA AP-607 Multi-Site Layout Planning with Intel's Flash FileTM Components ER-33 ETOXTM Flash Memory Technology - Insight to Intel's Fourth Generation Process Innovation Small and Low-Cost Power Supply solution for Intel's Flash Memory Products (Technical Paper) FLASHBuilder Design Resource Tool NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel's World Wide Web home page at http://www.Intel.com for technical documentation and tools. 55 |
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